1. Field of the Invention
The present invention relates to verification scenario generation and the verification of a bus system of a system LSI.
2. Description of the Related Art
Generally, in verifying a bus system of system large-scale integrations (LSI), whether data communication between an access-origin hardware block and an access-destination hardware block that are mutually accessible operates normally is checked based on a memory map. However, recently, verification of a bus system becomes difficult due to the increasingly large size and complexity of system LSIs. Therefore, the work load for and the work term for the verification work have increased and improved work efficiency by reducing the verification term is required.
To facilitate higher efficiency, for example, an approach has been proposed that realizes verification of a system LSI including a CPU, a memory, and a bus that connects the CPU and the memory, where verification is realized by a loop queue operation of an instruction queue included in the CPU (see, for example, International Patent Application Pamphlet No. 2002/073411). Thereby, a branching instruction is unnecessary because the same test program can be repeatedly executed and, therefore, the testing efficiency for a memory chip can be improved.
However, according to the above conventional technique, sufficient information to identify a path from an access origin to an access destination is not defined in a memory map. Therefore, a path necessary for generating a verification scenario can not be identified from the memory map. Thus, verification of data damage is insufficient for the case where plural accesses to an access destination occur, arising in a problem of the verification quality being degraded.
On the other hand, the extraction of path information from a design specification by a person who understands and verifies the design specification of the system LSI, etc, can be considered. However, the description contents of the design specification are compiled from the viewpoint of designing and, therefore, the extracting work of the path information may become difficult. Therefore, a problem arises in that the load on the person who does the verification is increased.
Due to the larger scale and greater complexity of system LSI, the number of paths connected to a specific access destination increases arising in the problem that covering all the paths manually is difficult. Furthermore, correction work of a circuit design becomes necessary as a result of oversights during verification and, therefore, increased load on the person who designs the circuit and extension of the design term are caused.